1. Field of the Invention
The present invention relates to an active matrix display device, and more particularly to a wiring structure of an active matrix display device comprising a light emitting element.
2. Description of the Related Art
In recent years, development of large-scale electroluminescence (hereinafter abbreviated to EL) display device has been advanced with the intention of coming to the television market.
When wiring length increases according to the increase in size of a display device, such problem as a voltage drop arises. There is a problem in that a voltage applied to each EL element varies with place by generation of the voltage drop so that display unevenness is caused.
In the case where film thickness of the wiring is increased in order to solve the above-mentioned problem, a lot of loads are applied to the steps of forming film, etching and the like. In addition, in the case where line width of the wiring is increased, the area ratio that the wiring occupies on the substrate is increased. Thus it makes difficult to fabricate a display device with high-definition.
With the increase in size of a display device, particularly in an active matrix display device, a variation in characteristics of thin film transistors (hereinafter referred to as TFTs) for transmitting an electric signal to an EL element on a substrate becomes large, leading to display unevenness.
Aiming to reduce the display unevenness due to the variation in characteristics of TFTs, a circuit for driving the EL element has been configured taking it into consideration (e.g., Patent Document 1). However, by providing a circuit for compensating for the variation in characteristics of TFTs, the ratio that the circuit occupies on the substrate is increased and the aperture ratio of a pixel portion is reduced.
[Patent Document 1]
    Japanese Laid-Open Patent Application No. 2003-5710
As described above, it is difficult to achieve the high-definition of a display device and the suppression of display unevenness due to a voltage drop in wirings or due to a variation in characteristics of TFTs at the same time.